Decoder for a trellis code

Pulse or digital communications – Systems using alternating or pulsating current – Plural channels for transmission of a single pulse train

Reexamination Certificate

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C714S792000

Reexamination Certificate

active

10781492

ABSTRACT:
The invention relates to trellis code decoder. The decoder comprises a path metrics calculation unit for calculating path metrics over at least two trellis columns in a trellis, and a memory for storing path metrics of the trellis. The decoder further comprises an input multiplexer connected between the read interface of the memory and the input interface of the path metrics calculation unit, and an output multiplexer connected between the output interface of the path metrics calculation unit and the write interface of the memory. The decoder further comprises a control for controlling configuration of the input multiplexer and configuration of the output multiplexer on the basis of states of the trellis, which state of the trellis defines the way the old path metrics and the new path metrics relate to each other, whereby internal configuration of the path metrics calculation unit remains the same for different code constraint lengths.

REFERENCES:
patent: 6504882 (2003-01-01), Kim
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patent: 2002/0162074 (2002-10-01), Bickerstaff
patent: 2006/0245487 (2006-11-01), Agazzi et al.
patent: 2006/0262832 (2006-11-01), Kaewell
patent: 1 102 408 (2001-05-01), None
patent: WO 01/78239 (2001-10-01), None
Hendrix, “Viterbi Decoding Techniques in the TMS320C54x Family”, Texas Instruments, Jun. 1996.
Black et al., “A Unified Approach to the Viterbi Algorithm State Metric Update for Shift Register Processes”, pp. 629-632, Mar. 1992.
Shung et al., Area-Efficient Architectures for the Viterbi Algorithm-Part I Theory, pp. 636-644, Apr. 1993.
Shung et al., Area-Efficient Architectures for the Viterbi Algorithm-Part II Applications, pp. 636-644, Apr. 1993.

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