Decoder for a non-volatile memory array using gate breakdown str

Details Decoder for a non-volatile memory array using gate breakdown str Decoder for a non-volatile memory array using gate breakdown str

1999-03-05

2000-04-25

Nelms, David

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365226, 365104, G11C 800

Patent

active

060552050

ABSTRACT:
A non-volatile memory cell is provided that includes a low voltage CMOS storage transistor having a source region and a drain region that are commonly connected to ground. The low voltage storage transistor is programmed by applying a high programming voltage to its gate, thereby rupturing the gate oxide of the storage transistor. The high programming voltage is applied to the low voltage storage transistor through a high voltage p-channel transistor. The high voltage p-channel transistor has a thicker gate oxide than the storage transistor, thereby enabling the p-channel transistor to withstand higher voltages. The high voltage p-channel transistor also has a higher breakdown voltage than a high voltage n-channel transistor of the same size. Both the low voltage storage transistor and the high voltage p-channel transistor are fabricated in accordance with a standard sub 0.35 micron process. The state of the low voltage storage transistor can be read through the p-channel transistor, or through a dedicated high voltage n-channel transistor. In one embodiment, the programming voltage is generated by a charge pump circuit fabricated in accordance with a standard sub 0.35 micron process. In another embodiment, the decoder circuits that access the non-volatile memory cell use high voltage p-channel transistors to transmit the high programming voltage. Another embodiment of the present invention includes a system-on-a-chip structure that implements the non-volatile memory of the present invention.

REFERENCES:
patent: 4689504 (1987-08-01), Raghunathan et al.
patent: 5563842 (1996-10-01), Challa
patent: 5796656 (1998-08-01), Kowshik et al.
patent: 5812459 (1998-09-01), Atsumi et al.
Ying Shi; T. P. Ma; Sharad Prasad; an Sumit Dhanda, "Polarity Dependent Gate Tunneling Currents in Dual-Gate CMOSFET's", IEEE Transactions on Electron Devices, vol. 45, No. 11, Nov. 1998, pp. 2355-2360.

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