Static information storage and retrieval – Floating gate – Particular biasing
Patent
1988-10-17
1991-05-14
Bowler, Alyssa H.
Static information storage and retrieval
Floating gate
Particular biasing
36523006, 36523004, 365 51, 36523002, G11C 700, G11C 1604, G11C 800
Patent
active
050162160
ABSTRACT:
An array of floating gate transistors is arranged so that in the transistors within the even numbered rows, the bit line on the left side of the transistor serves as the drain, and the bit line on the right side of the transistor serves as the source, and the floating gate extends over the left side of the transistor channel. Conversely, in the odd numbered rows, the bit line on the right side of each transistor serves as the drain, the bit line on the left side of each transistor serves as the source, and the floating gate extends over the left side of the transistor channel. Thus, in order for the bit line decoder to determine which bit line is to be grounded and which bit line is to be connected to a sense amplifier, the bit line decoder also receives signals indicative of the row which has been addressed. In one embodiment, the array comprises redundant rows. The decoder is constructed so that any redundant rows can be used to replace either an odd or even-numbered row in the array. The array also includes a dummy transistor column. Means are provided for coupling a transistor from the dummy transistor column to the sense amplifier which has a floating gate on the same side of the channel as a transistor being read. Decode means are provided for coupling each dummy bit line to either ground or the sense amplifier.
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Ali, "A 50-ns 256K CMOS Split-Gate EPROM," IEEE Journal of Solid-State Circuits, vol. 23, No. 1, Feb. 1988, pp. 79-85.
Bowler Alyssa H.
Waferscale Integration Inc.
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