Decoder for a compressed digital video signal using a common mem

Television – Bandwidth reduction system

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H04N 732

Patent

active

055636608

ABSTRACT:
An apparatus for expanding a compressed digital video signal representing a motion picture to provide a digital video output signal. The compressed digital video signal comprises plural interlaced frames with a frame rate of 24 Hz. The digital video output signal comprises plural pictures with a picture rate of at least 49 Hz. The apparatus includes a frame memory comprising no more than four pages, each page storing one frame. The apparatus also includes an expander for expanding the compressed digital video signal to derive a reconstructed interlaced frame from each frame of the compressed digital video signal. Finally, the apparatus includes a controller that controls writing of each reconstructed interlaced frame into one page of the frame memory. The controller also controls reading out of the reconstructed interlaced frames stored in the pages of the frame memory to provide the pictures of the digital video output signal. Reading out is controlled to effect 2-3 pull down conversion of the reconstructed interlaced frames stored in the frame memory with a frame rate of 24 Hz to provide the pictures of the digital video output signal with a picture rate of at least 49 Hz.

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