Coded data generation or conversion – Converter compensation
Patent
1988-03-31
1991-06-11
Shoop, Jr., William M.
Coded data generation or conversion
Converter compensation
341159, H03M 106
Patent
active
050236130
ABSTRACT:
There is disclosed a decoder configuration for a high-speed flash-type analog-to-digital converter which utilizes a plurality of comparators arranged from a first lower order comparator to a last high order comparator based on the particular position of each comparator as coupled to taps of a reference resistance ladder. The measurement point in such a system can be logically decoded by establishing the tap where all comparators below it are low and ideally all comparators above the tap are high. This is implemented in a decoding scheme which implements the test by testing all combinations of three adjacent comparators so that the selected tap is high and the taps immediately above and below it are high and low respectively to therefore detect an HHL sequence. In regard to the present invention, there are included means which will prevent a higher order HHL sequence from appearing when a lower order HHL sequence is detected. In this manner by inhibiting a higher state reading with a lower state reading, one can prevent serious errors which would undesirably cause a "sparkle" in the decoded output signal.
REFERENCES:
patent: 4591825 (1986-05-01), Bucklen
patent: 4774498 (1988-09-01), Traa
Harris Semiconductor (Patents) Inc.
Hoff Marc S.
Schanzer Henry I.
Shoop Jr. William M.
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