Decoder driver circuit for programming high-capacitance lines

Details Decoder driver circuit for programming high-capacitance lines Decoder driver circuit for programming high-capacitance lines

1988-02-01

1989-04-11

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307452, 307475, 307264, 365226, H03K 1710

Patent

active

048209414

ABSTRACT:
A driver circuit for applying both read and program voltages to a wordline of an integrated-circuit memory-cell logic array. The driver circuit is comprised of a series driver transistor pair, of a driver enabling means for enabling and disenabling one of the transistors of the driver transistor pair, and of a latching means. The driver transistor used during read operation may be constructed with a relatively short source-drain channel, permitting faster access speed during read operation of the circuit.

REFERENCES:
patent: 4441172 (1984-04-01), Ebel
patent: 4442481 (1984-04-01), Brahmbhatt
patent: 4471240 (1984-09-01), Novorel
patent: 4565932 (1986-01-01), Kuo et al.
patent: 4574273 (1986-03-01), Atsumi et al.
patent: 4616143 (1986-10-01), Miyamoto
patent: 4651029 (1987-03-01), Oritani
patent: 4692638 (1987-09-01), Stiegler
patent: 4710900 (1987-12-01), Higuchi
patent: 4767950 (1988-08-01), Schrenk

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