Decoder circuitry with reduced number of inverters and bus lines

Details Decoder circuitry with reduced number of inverters and bus lines Decoder circuitry with reduced number of inverters and bus lines

1986-11-26

1988-07-19

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307463, H03K 19094

Patent

active

047587440

ABSTRACT:
A decoder circuit for fully decoding N input variables includes 2.sup.N logic gates arranged into 2.sup.N-1 pairs of gates, with each gate having N inputs, and one output. The decoder also includes (N-1) inverters for producing the complements of N-1 of the N input variables whereby the (N-1) input variables and their complements are arranged into 2.sup.(N-1) different combinations of (N-1) signals for generating a different combination of (N-1) signals per pair of logic gates. (N-1) inputs of each of the two gates forming a pair of gates are interconnected to receive the same N-1 input signals forming one of the 2.sup.N-1 combinations. The Nth input variable is applied to the Nth input of one gate from each pair of gates and the output of the one gate from each pair is connected to the Nth input of the other gate with which it is paired.

REFERENCES:
patent: 4259731 (1981-03-01), Moench
patent: 4292547 (1981-09-01), Pfiester et al.
patent: 4309629 (1982-01-01), Kamuro
patent: 4479126 (1984-10-01), Higuchi et al.
patent: 4538247 (1985-08-01), Venkateswaran
patent: 4583205 (1986-04-01), Watanabe
patent: 4620117 (1986-10-01), Fang
patent: 4631425 (1986-12-01), Koshimaru
patent: 4633220 (1986-12-01), Burgess
patent: 4684829 (1987-08-01), Uratani
Lipa, "Low Power CMOS NOR Decoder for Automatically Powering Down Unselected Decoders", IBM T.D.B., vol. 27, No. 6, Nov. 1984, pp. 3203-3204.
Moore et al., "Metal Oxide Transistor Decode Circuit" IBM T.D.B., vol. 9, No. 6, Nov. 1966, pp. 703-704.

Affiliated with

Also associated with

Rating

Decoder circuitry with reduced number of inverters and bus lines does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Decoder circuitry with reduced number of inverters and bus lines, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Decoder circuitry with reduced number of inverters and bus lines will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-598943