Decoder circuit with bypass circuitry and reduced input capacita

Details Decoder circuit with bypass circuitry and reduced input capacita Decoder circuit with bypass circuitry and reduced input capacita

1992-03-09

1993-11-16

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307449, 307443, H03K 1920, H03K 19096

Patent

active

052626873

ABSTRACT:
An address detection circuit is described having a node A which is precharged to the voltage of a power supply and then discharged down to ground by a strobe signal if an address match occurs. An address match is detected when a nonconventional CMOS inverter which has its input connected to node A has its output go HIGH. The nonconventional CMOS inverter utilizes a device ratio between its P-mos transistor and its N-mos transistor of approximately 10 to 1 for a 1 micron CMOS process. Prior to the strobe signal discharging the node A to ground, the output of the nonconventional inverter is held to ground by a transistor which is switched OFF when the strobe signal discharging the node A to ground is initiated.

REFERENCES:
patent: 3989955 (1976-11-01), Suzuki
patent: 4401903 (1983-08-01), Iizuka
patent: 4415819 (1983-11-01), Mathes
patent: 4692639 (1987-09-01), Jordan
patent: 4918663 (1990-04-01), Remington et al.
patent: 4974241 (1990-11-01), McClure et al.

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