Decoder circuit used in a flash memory device

Details Decoder circuit used in a flash memory device Decoder circuit used in a flash memory device

2005-03-22

2005-03-22

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185170, C365S185230, C365S185330

Reexamination Certificate

active

06870769

ABSTRACT:
A decoder circuit according to the present invention comprises a global row decoder consisted of a first decoding means selected according to a row address signal and a second decoding means to which an output signal of the first decoding means and an erasure signal are input and a local row decoder for selecting each global word line signal outputted from the global row decoder. The local row decoder is consisted of a first and second transistors to the word line signal is input, and a third, fourth and fifth transistors outputting a first voltage supply signal and a second voltage supply signal to a sector word line.

REFERENCES:
patent: 5193074 (1993-03-01), Anami
patent: 5546352 (1996-08-01), Sato et al.
patent: 5621690 (1997-04-01), Jungroth et al.
patent: 5717636 (1998-02-01), Dallabora et al.

Affiliated with

Also associated with

Rating

Decoder circuit used in a flash memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Decoder circuit used in a flash memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Decoder circuit used in a flash memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3368758