Decoder circuit of erasable programmable read only memory for av

Details Decoder circuit of erasable programmable read only memory for av Decoder circuit of erasable programmable read only memory for av

1990-09-18

1991-08-06

Clawson, Jr., Joseph E.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365185, 307443, 307449, 307452, 307481, G11C 802

Patent

active

050383272

ABSTRACT:
A load unit is connected between a high potential power supply line and a decoded output terminal, a plurality of decoder transistors are connected in series between the decoded output terminal and a low potential power supply line, and gates of the decoder transistors are supplied with input signals. A current supply unit is connected to at least one of a plurality of connection points of the decoder transistors, so that capacitors parasitically formed at the connection points of the decoder transistors are not only charged by a current from the load unit, but also charged by a current from a current from the current supply unit. Therefore, an erroneous operation of the decoder circuit caused by the parasitic capacitors can be avoided without increasing the access time and power consumption thereof.

REFERENCES:
patent: 4700086 (1987-10-01), Ling et al.
patent: 4780626 (1988-10-01), Guerin et al.
patent: 4827160 (1989-05-01), Okano

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