Decoder circuit having CMOS inverter circuits

Details Decoder circuit having CMOS inverter circuits Decoder circuit having CMOS inverter circuits

1994-03-17

1995-08-29

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, 36523001, 326104, 326105, G11C 1134

Patent

active

054467004

ABSTRACT:
A decoder circuit comprises a plurality of input word select lines, a plurality of input block select lines, a main decoder, and a plurality of CMOS inverters each having a first power source node, a second power source node applied with a predetermined potential, an input node connected to one of the input word select lines, and a decoder output line. The main decoder activates/deactivates each CMOS inverter by applying an output signal to the first power source node of each CMOS inverter, thereby driving each decoder output line according to the logic level of the respective input word select line when the CMOS inverter is activated. The decoder circuit also includes means for controlling the logic level of the output block select lines according to the logic levels of the input block select lines.

REFERENCES:
patent: 4723229 (1988-02-01), Hartgring et al.
patent: 4837747 (1989-06-01), Dosaka et al.
patent: 4843261 (1989-06-01), Chappell et al.
patent: 4939696 (1990-07-01), Katsuo et al.
patent: 4951259 (1990-08-01), Sato et al.
patent: 4972373 (1990-11-01), Kim et al.

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