Decoder circuit having a variable power supply

Details Decoder circuit having a variable power supply Decoder circuit having a variable power supply

1985-07-29

1988-11-01

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307450, 307451, 307463, 365184, G11C 8000, G11C 1134, H03K 19017

Patent

active

047822473

ABSTRACT:
A decoder circuit fabricated in an IC memory chip and provided to respective word-lines and respective bit-lines of an IC memory matrix fabricated in the IC memory chip, is provided for selecting an EPROM cell which is placed on an intersection point of the word-line and the bit-line, to program a datum into the EPROM cell by using a high power supply voltage when the decoder circuit operates under a programming mode and to read out a datum stored in the EPROM cell by using a low power supply voltage when the decoder circuit operates under a reading mode, receiving an address signal from the exterior of the decoder circuit. The decoder circuit comprises a NAND gate having its load and a CMOS invertor. In making the load of the NAND gate function as a constant current load, only a variable power supply voltage, which becomes a high and a low voltage according to the programming and the reading mode respectively, can be applied to the decoder circuit without using other elements such as a transfer gate and a compensator as required in the prior art.

REFERENCES:
patent: 3982138 (1976-09-01), Luisi et al.
patent: 3995171 (1976-11-01), Sonoda
patent: 4374430 (1983-02-01), Higuchi
patent: 4415993 (1983-11-01), Smith et al.
patent: 4443718 (1984-04-01), Hagiwara et al.
8107 IEEE Journal of Solid-State Circuits, vol. SC-18(1983), Oct., No. 5, New York, USA "A High-Speed Ultra-Low Power 64K CMOS EPROM with On-Chip Test Functions". pp. 554-561.

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