Decoder circuit having a predecoder acitivated by a reset signal

Details Decoder circuit having a predecoder acitivated by a reset signal Decoder circuit having a predecoder acitivated by a reset signal

1997-01-17

1998-08-04

Fears, Terrell W.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518905, 36523008, G11C 1300

Patent

active

057904707

ABSTRACT:
A decoder circuit prevented from multi-selection is disclosed. The decoder circuit has a pulse generator receiving an external clock signal and outputting a reset signal in response to the external clock signal, address counters receiving the external clock signal and outputting address count signals and address buffers coupled to the address counters respectively. Each of the address buffers receives an external address signal and the address count signal and outputs an internal address signal. The decoder circuit further has address predecoders coupled to the pulse generator and said address buffers. Each of the address predecoders decodes the internal address signals to output a predecode signal in response to the reset signal. The decoder circuit further has an address decoder coupled to the address predecoders. The address decoder decodes the predecode signals to output decode signals.

REFERENCES:
patent: 5148397 (1992-09-01), Kokbun

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