Decoder circuit for phase modulated signals

Details Decoder circuit for phase modulated signals Decoder circuit for phase modulated signals

1993-06-11

1995-08-29

Chin, Stephen

Pulse or digital communications

Receivers

Automatic baseline or threshold adjustment

327 51, 375324, 375345, 4552321, 4552401, 329318, H03D 300, H03K 906

Patent

active

054467616

ABSTRACT:
A decoder circuit (21) and method for providing an amplitude compensated signal by removing the undesired effect of amplitude modulation on a phase modulated signal. The decoder method is provided by demodulating a received inphase receive signal component (10) and quadrature receive signal component (12) of the phase modulated signal and outputting an amplitude varying signal (15) to a feedforward automatic gain control circuit that outputs an amplitude compensated signal (38). The feedforward automatic gain control circuit comprises a detector circuit (16), an offset bias circuit (32), a differencer circuit (30) and a gain control circuit (28).
The detector circuit (16) outputs a DC signal (17) representing an amplitude of the inphase receive signal (10) and the quadrature receive signal (12). The offset bias circuit (32) provides a constant current bias (29) to the DC signal (17) thus creating a control signal 31. The gain control circuit (28) receives the control signal (31) and the amplitude varying signal (15) and outputs an amplitude compensated signal (38).

REFERENCES:
patent: 4631489 (1986-12-01), Laird et al.
patent: 4675882 (1987-06-01), Lillie et al.
patent: 4910467 (1990-03-01), Leitch
patent: 5291525 (1994-03-01), Funderburk et al.

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