Decoder circuit for MOS memory of a redundant structure

Details Decoder circuit for MOS memory of a redundant structure Decoder circuit for MOS memory of a redundant structure

1984-12-10

1987-03-17

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307200B, 3072021, 307441, 307463, 307468, H03K 19003, H03K 19096

Patent

active

046510303

ABSTRACT:
A decoder circuit for MOS memory of a redundant structure having shorter delays in access time contains a programmable element in a redundant circuit rather than connected in series on the word line driving signal.

REFERENCES:
patent: 4051388 (1977-09-01), Inukai
patent: 4399372 (1983-08-01), Tanimoto et al.
patent: 4455495 (1984-06-01), Masuhara et al.
patent: 4546455 (1985-10-01), Iwahashi et al.
Tolley et al., "72-K RAM Stands Up to Soft and Hard Errors", Electronics, Jun. 1982, pp. 147-151.
Sud et al., "Designing Static RAMs for Yield as Well as Speed", Electronics, Jul. 1981, pp. 121-126.

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