Decoder circuit for generating a system clock signal phase locke

Details Decoder circuit for generating a system clock signal phase locke Decoder circuit for generating a system clock signal phase locke

1994-05-13

1995-09-12

Groody, James J.

Television

Synchronization

348507, 348537, 375376, H04N 1700, H04N 945

Patent

active

054501369

ABSTRACT:
A decoder circuit for receiving a video input signal which includes Manchester coded data bits and a range tone component having a frequency of about 102.6 kilohertz. A phase lock loop circuit detects the presence of the 102.6 kilohertz range tone component and then generates a system clock signal which is phase locked to the range tone component of the video input signal. The system clock signal is provided to a clock generating circuit which generates a clock signal having four phases. The phase lock loop circuit also provides a logic signal which is supplied to a data detecting circuit allowing the data detecting circuit to convert the Manchester coded data bits to digital data bits.

REFERENCES:
patent: 4118738 (1978-10-01), Arnstein
patent: 4584695 (1986-04-01), Wong et al.
patent: 4713841 (1987-12-01), Porter et al.
patent: 4837781 (1989-06-01), Hickling
patent: 4853943 (1989-08-01), Laws
patent: 5235422 (1993-08-01), Ido et al.
Excerpts from Navair 16-30DKW3A-1 Maintanence Manual, pp. 2, 5, 6, 16, 25 d 26 and Figs. 4, 6 and 8.

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