Communications: electrical – Digital comparator systems
Patent
1977-08-12
1979-01-16
Yusko, Donald J.
Communications: electrical
Digital comparator systems
340168B, 340171R, 340311, 179 84VF, H04Q 914
Patent
active
041351509
ABSTRACT:
A decoder circuit for receiving a sequence of coded digit signals and detecting when a preselected digit signal sequence is received includes a converter having a plurality of converter outputs which are energized in response to receipt of each of the coded digit signals. A plurality of digit sequence selection lines are connected to predetermined ones of the converter outputs in dependence upon the preselected digit signal sequence. A plurality of coincidence gates are provided with each of the gates responsive to one of the digit sequence selection lines. A shift register provides a means for enabling each of the coincidence gates in a sequence which corresponds to the predetermined digit sequence. The outputs of the coincidence gates are applied to the shift register shift input to cause the register to shift and enable the next gate in succession. Means are provided for detecting when each of the coincidence gates associated with the preselected digit selection lines has provided an output pulse. Additionally, ALL CALL and GROUP CALL modes of operation are provided in which less than the entire sequence of coded digit signals are needed to cause the decoder circuit to detect receipt of the digit signals.
REFERENCES:
patent: 3629847 (1971-12-01), Adlhoch
patent: 3934097 (1976-01-01), Carbrey
patent: 4001772 (1977-01-01), Powell et al.
Ledex Inc.
Yusko Donald J.
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