Decoder circuit arrangement with MOS transistors

Details Decoder circuit arrangement with MOS transistors Decoder circuit arrangement with MOS transistors

1977-08-17

1979-03-20

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307205, 307215, 307DIG4, 307DIG5, 365230, H03K 1908, H03K 1934, G11C 800, H03K 5153

Patent

active

041456220

ABSTRACT:
A decoder circuit arrangement with MOS transistors includes a decoder circuit and an output stage. The output stage includes a driver transistor which emits a selection signal, in accordance with a decoder signal emitted from the decoder circuit, and includes a shunt transistor having a controlled path connected between the output of the decoder circuit and the output of the output stage and a control input which is supplied with the selection signal. An additional transistor has a controlled path connected between the output of the output stage and a fixed potential and a control input which is driven by a timing signal which renders the additional transistor conductive, at least during the time in which the selection signal is not present.

REFERENCES:
patent: 3702926 (1972-11-01), Picciano et al.
patent: 3718826 (1973-02-01), Donofrio et al.
patent: 3795898 (1974-03-01), Mehta et al.
patent: 3959781 (1976-05-01), Mehta et al.
patent: 3986054 (1976-10-01), Hansen et al.
patent: 3995171 (1976-11-01), Sonoda et al.
patent: 4001601 (1977-01-01), Schuster
patent: 4011549 (1977-03-01), Bormann
patent: 4027174 (1977-05-01), Ogata
patent: 4048629 (1977-09-01), Bormann
patent: 4063118 (1977-12-01), Nishimura
Remshardt et al., IEEE Journal of Solid-State Circuits, vol. SC-11, No. 3, pp. 352-358; Jun. 1976.
SIMI, "Field-Effect Transistor Drive Circuit"; IBM Tech. Discl. Bull.; vol. 17, No. 4, p. 1120; Sep. 1974.

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