Decoder circuit, and photo-detecting amplifier circuit and...

Dynamic information storage or retrieval – Control of storage or retrieval operation by a control... – Control of information signal processing channel

Reexamination Certificate

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Reexamination Certificate

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07321530

ABSTRACT:
A decoder circuit of the present invention, mounted on an integrated circuit, decodes input voltage Vin supplied to a single external input terminal into three or more control outputs, and an object of the present invention is to reduce the size of a chip. The foregoing decoder circuit includes: a P-type transistor in which an emitter is connected to a power source line of high level, a base is connected to the external input terminal, and a collector is an output terminal of a first control output; and an N-type transistor in which an emitter is connected to a power source line of low level, a base is connected to the external input terminal, and a collector is an output terminal of a second control output, and decodes the control outputs to three or more sets of data by carrying out logic operations. Therefore, as compared to the case of using a comparator requiring many transistors, a constant current source, and other elements, one each transistor is required for each of the two control outputs to be generated. This facilitates size reduction of a chip.

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patent: 4465944 (1984-08-01), Shin
patent: 5039882 (1991-08-01), Arakawa
patent: 5418762 (1995-05-01), Kitayama
patent: 5638029 (1997-06-01), O'Shaughnessy
patent: 5854772 (1998-12-01), Suzu
patent: 5999464 (1999-12-01), Hidaka et al.
patent: 60-062239 (1985-04-01), None
patent: 61-182327 (1986-08-01), None
patent: 2-6684 (1990-02-01), None
patent: 06-090126 (1994-03-01), None
patent: 2000-236251 (2000-08-01), None

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