Decoder circuit and decoding method of the same

Details Decoder circuit and decoding method of the same Decoder circuit and decoding method of the same

1999-11-16

2001-05-29

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Utilizing three or more electrode solid-state device

C327S108000, C327S437000, C327S111000

Reexamination Certificate

active

06239647

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a decoder circuit and decoding method thereof, and more particularly to a decoder circuit and decoding method thereof which decoder circuit is included in a semiconductor integrated circuit (IC).
2. Description of the Related Art
Nowadays, in a semiconductor IC, device dimensions are being minimized and the volume of their memory is being increased year by year. Accordingly, in order to make the semiconductor IC have a higher speed, it is needed to realize minimization (hereinafter “minimization” refers to minimization of dimensions) of memory cells (referred to as “MC” hereinafter) thereof and, minimization and high speed of circuits disposed around the MC.
FIG. 1
shows an example for illustrating the circuits disposed around the MC. In this diagram, based on decoder-circuit selecting signals supplied by an address decoder
10
and clock signals supplied by a clock buffer
20
, decoder circuits
30
-
1
to
30
-n are selected so as to generate respective word line signals WL
1
to WLn.
The address decoder
10
is supplied with memory address signals A
0
to Am from an outside portion (not shown), and generates the decoder-circuit selecting signals based on these memory address signals A
0
to Am. For example, the address decoder
10
generates a decoder-circuit selecting signal for selecting the decoder circuit
30
-
1
in a case in which a memory address signal indicates a memory address controlled by the word line WL
1
outputted from the decoder circuit
30
-
1
.
Next, the decoder circuits
30
-
1
to
30
-n are described with reference to
FIG. 2
showing an example of these decoder circuits. As seen from this diagram, each of the decoder circuits
30
-
1
to
30
-n includes a NAND circuit
31
and NOT circuits
32
to
34
. The NAND circuit
31
is supplied with two decoder-circuit selecting signals and a clock signal, and, for example, when the three supplied signals are all high, a high-level word line signal is outputted from the NOT circuit
34
.
However, in these conventional decoder circuits, there is a problem that, as the volume of the memory of the MC is increased, a load increases over lines through which the decoder-circuit selecting signals for selecting the decoder circuits pass. Furthermore, in order to realize a higher speed of the semiconductor IC, it is needed to minimize the MC, and minimize and make high speed the circuits disposed around the MC, of which circuits the decoder circuits are particularly desired to be minimized.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a decoder circuit and decoding method, in which the above disadvantages are eliminated.
A more specific object of the present invention is to provide a decoder circuit and decoding method, in which a load over decoder-circuit selecting signal lines can be reduced and the number of stages of logic circuits, forming a decoder circuit, can be decreased.
The above objects of the present invention are achieved by a decoder circuit a decoder circuit comprising: a detecting device which detects a selecting signal for selecting the decoder circuit; a clock-signal supplying device which supplies a clock signal; and a decoded signal outputting device which outputs a decoded signal according to timing of the clock signal when said detecting device detects the selecting signal.
The above objects of the present invention are also achieved by a decoder circuit comprising: a NOR logic circuit which detects a selecting signal for selecting the decoder circuit; a NOT logic circuit which inverts a clock signal and outputs an inverted clock signal; a first PMOS transistor which is set in an ON state when the selecting signal is detected; and a second NMOS transistor which is set in an ON/OFF state according to timing of the inverted clock signal outputted from the NOT logic circuit. When the selecting signal is detected, a decoded signal is outputted based on states of the first PMOS transistor and the second NMOS transistor.
The above-mentioned objects of the present invention are also achieved by decoder circuit comprising: a first PMOS transistor and a first NMOS transistor which detect respective selecting signals for selecting the decoder circuit; a NOT logic circuit which inputs a clock signal and outputs an inverted clock signal; a second PMOS transistor which is set in an ON state when the selecting signal is detected; and a second NMOS transistor which is set in an ON/OFF state according to timing of the inverted clock signal outputted from the NOT logic circuit. When the respective selecting signals are detected, a decoded signal is outputted based on states of the second PMOS transistor and the second NMOS transistor.
The above-mentioned objects of the present application are also achieved by a decoding method comprising the steps of: a) detecting a selecting signal for selecting the decoder circuit; b) supplying a clock signal; and c) outputting a word line signal according to timing of the clock signal when the selecting signal is detected.
The above-mentioned objects of the present invention are also achieved by A decoding method comprising the steps of: a) detecting a selecting signal for selecting the decoder circuit; b) receiving a clock signal and supplying an inverted clock signal; c) setting a first PMOS transistor in an ON state when the selecting signal is detected; d) setting a second NMOS transistor in an ON/OFF state according to timing of the inverted clock signal; and e) outputting a word line signal based on the states of the first PMOS transistor and said second NMOS transistor, when the selecting signal is detected.


REFERENCES:
patent: 5680343 (1997-10-01), Kamaya

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