Decoder circuit

Details Decoder circuit Decoder circuit

1983-09-26

1986-02-18

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307463, H03K 1920, H03K 19017, H03K 19096, G11C 800

Patent

active

045715106

ABSTRACT:
A decoder circuit receives decoder inputs and producing decoder outputs. The decoder inputs are applied, as control inputs, to respective input transistors connected in parallel with each other. The outputs thereof are commonly connected to a node. The node is connected to a gate transistor and latch transistors. The gate transistor is operative to invert the level at the node momentarily every time the decoder circuit is switched from a nonselection state to a selection state. The latch transistors maintain the level at the node as the decoder output level.

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patent: 4398102 (1983-08-01), Stewart
patent: 4404474 (1983-09-01), Dingwall
patent: 4455629 (1984-06-01), Suzuki et al.
Schlageter et al., "Two 4K Static 5-VRAM's"; IEEE-JSSC, vol. SC-11, No. 5, pp. 602-608; 10/1976.
Schuster, "On-Chip Redundancy Scheme"; IBM Tech. Discl. Bull.; vol. 14, No. 5, pp. 1513-1514; 10/1971.
Pashley et al., "A 16K.times.1B Static RAM"; IEEE ISSCC'79-2/15/79, Digest of Technical Papers.
IEEE Journal of Solid-State Circuits, "2K.times.8 Bit Hi-CMOS Static RAM's", Osamu Minato et al., vol. SC-15, No. 4, Aug. 1980, pp. 656-660.

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