Decoder circuit

Details Decoder circuit Decoder circuit

1991-02-26

1992-10-27

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072968, 36518909, 36523006, H03K 19094, G11C 8000

Patent

active

051592150

ABSTRACT:
A decoder circuit comprises a P type substrate in which an N well is formed, a plurality of P channel word line drive transistors each having a gate supplied with a signal having a level corresponding to an address signal and a source-drain connected between a word line and an input terminal of a signal driving the word line and the N well is biased with a biasing signal different from said word line drive signal. Gate insulating films of the word line drive transisters are not subjected to breakdown by a high voltage application thereto. Further, since there is no extra load applied to the clock signal, it is possible to make the word line drive at high speed.

REFERENCES:
patent: 4233672 (1980-11-01), Suzuki et al.
patent: 4618784 (1986-10-01), Chappell et al.
patent: 4760560 (1988-07-01), Arlizumi
patent: 4802123 (1989-01-01), Tobita
patent: 4843261 (1989-06-01), Chappell et al.
patent: 4862415 (1989-08-01), Nakano
patent: 4918663 (1990-04-01), Remmington et al.
patent: 4982372 (1991-01-01), Matsuo
patent: 5051959 (1991-09-01), Nakano et al.

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