Decoder circuit

Details Decoder circuit Decoder circuit

1999-07-30

2001-06-12

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185110

Reexamination Certificate

active

06246609

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates generally to semiconductor devices, and more particularly to a decoder circuit for semiconductor devices, especially non-volatile semiconductor memory devices such as flash memory devices.
Generally, a flash memory device comprises an address sequencer, row and column decoders, sense amplifiers, write amplifiers, and a memory cell array. An example of a flash memory device is described in U.S. Pat. No. 5,490,107, the disclosure of which is herein incorporated by reference. The memory cell array contains a plurality of memory cells arranged in rows and columns. Each memory cell is capable of holding a single bit of information. A column of memory cells in the memory cell array is commonly coupled to a bit line. The column decoder along with the address sequencer selects a bit line. Similarly, the memory cells arranged in a row of the memory cell array are commonly coupled to a word line. The row decoder and address sequencer selects a word line. Together the row and column decoders and the address sequencer selects an individual memory cell or a group of memory cells.
The memory cells in the memory cell array of a flash memory device are generally grouped into sub-arrays called memory cell blocks. Each memory cell block is coupled to a sense amplifier and a write amplifier. The write amplifier (W/A) applies a set of predetermined voltages to store information in the selected memory cells. This action is referred to as a program or write operation. Similarly, a set of predetermined voltages applied to the selected memory cells allows information to be discriminated and retrieved by the sense amplifier (S/A). This action is referred to as a read operation.
During a write or program operation, relatively high program voltage V
pp
needs to be supplied by the decoder circuits to the memory cells. Since the decoder circuits must handle V
pp
, high voltage transistors must be used in the decoder circuits. However, high voltage transistors have a thick oxide layer and thus operate slower than lower voltage transistors.
Therefore, in order to increase the speed of program and read operations, it would be advantageous to use lower voltage transistors. Since high voltage transistors are necessary in the decoder circuit to handle V
pp
, it would be beneficial to separate the high voltage portion of the decoder circuit from the lower voltage portion. If most of the logical switching is handled by the low voltage portion in the decoder circuits, the flash memory device with an increased capability for faster read and program operation would result.
SUMMARY OF THE INVENTION
The present invention provides a decoder circuit. The decoder circuit comprises a gate voltage provider circuit and a gate voltage selection circuit. The gate voltage provider circuit receives a plurality of address signals and a gate voltage and provides the gate voltage as an output. Also, the gate voltage provider circuit provides the gate voltage output when the address signals indicate conditions are met for generating the gate voltage output. The gate voltage selection circuit provides the gate voltage to the gate voltage provider circuit for use as the output of the gate voltage provider circuit.
Many of the attendant features of this invention will be more readily appreciated as the same becomes better understood by reference to the following detailed description and considered in connection with the accompanying drawings in which like reference symbols designate like parts throughout.


REFERENCES:
patent: 5910913 (1999-06-01), Kato et al.

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