Decoder checking circuits suitable for semiconductor memories

Details Decoder checking circuits suitable for semiconductor memories Decoder checking circuits suitable for semiconductor memories

1991-07-10

1994-07-19

Beausoliel, Jr., Robert W.

Excavating

371 27, G01R 3128

Patent

active

053316444

ABSTRACT:
A decoder checking circuit for testing a decoder in a semiconductor memory device, comprising an address signal generator for generating a test address signal, a first switch for transferring selectively either the address signal or the test address signal, to a decoder, a second switch for transferring the output of the decoder to the memory cell array, an expected value generator for generating an expected value for the output of the decoder, and a comparing circuit for comparing the output of the second switch with the expected value.

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patent: 5271015 (1993-12-01), Akiyama
Jacob Millman et al. Microelectronics 1987 p. 276, p. 313, pp. 325-331.

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