Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2002-05-02
2004-08-24
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C345S092000, C345S204000
Reexamination Certificate
active
06781535
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a decoding apparatus and, more particularly, to a decoder capable of being employed in a Resistance-array Digital/Analog (RDA) converting apparatus in a Thin-Film Transistor Liquid Crystal Display (TFT-LCD) driver integrated circuit (IC).
DESCRIPTION OF THE PRIOR ART
FIG. 1
is a diagram illustrating a typical TFT-LCD. The TFT-LCD includes a timing control unit
100
, an LCD panel
400
, a plurality of gate drivers
200
and a plurality of source drivers.
The plurality of gate drivers
200
are driven by the timing control unit
100
and drive the gate lines of the LCD panel
400
. The plurality of source drivers
300
, also driven by the timing control unit
100
, drive the source lines of the LCD panel
400
so that the LCD panel
400
displays data.
The LCD panel
400
comprises pixels arrayed in a matrix. Each pixel includes an LCD capacitor (C
1
) and a thin film transistor (T
1
). A source of the thin film transistor (T
1
) is connected to a source line driven by one of the source drivers
300
and a gate of the thin film transistor is connected to a gate line driven by one of the gate drivers
200
.
The timing control unit
100
drives the gate lines assigned to the gate driver (
200
), sequentially one-by-one. The source driver
300
receives data from the timing control unit
100
and applies analog signals to the source lines so that the data is displayed on the TFT-LCD.
FIG. 2
is a diagram illustrating a source driver in the TFT-LCD. The source driver includes a digital controlling unit
310
, a registering unit
320
, a level-shifting unit
330
, a digital/analog converting unit
340
, an analog bias unit
350
and a buffering unit
360
. The registering unit
320
is generally driven at a low voltage level, such as 3.3V, and the digital/analog converting unit
340
and the buffering unit
360
are generally driven at a high voltage level, such as 6-12V.
The digital controlling unit
310
controls the registering unit
320
. The digital controlling unit
310
receives source start pulses (SSP), data clocks and digital data from the timing control unit
100
in FIG.
1
and transmits the digital data to the registering unit
320
.
The registering unit
320
stores digital data from the digital controlling unit
310
. The registering unit
320
includes a shift registering unit
321
, a sample registering unit
322
and a hold registering unit
323
. All of the digital data is routed through the shift registering unit
321
and stored in the sample registering unit
322
. The digital data stored in the sample registering unit
322
is transmitted through the hold registering unit
323
to the level-shifting unit
330
via control signals (LOAD) provided by the timing control unit
100
. The level-shifting unit
330
shifts the levels of the digital signals from the registering unit
320
and provides the level-shifted digital signals to the digital/analog converting unit
340
.
The digital/analog converting unit
340
converts the level-shifted digital signals into analog signals. The digital/analog converting unit
340
includes a gamma reference unit
342
and a decoding unit
344
. The decoding unit
344
outputs an analog signal, which is one of the analog signals of the gamma reference unit
342
, in response to a select signal. The select signal is a digital signal passed through the level shifting unit
330
. The buffering unit
360
buffers the outputs of the digital/analog converting unit
340
by the bias provided by the analog bias unit
350
and provides the buffered outputs to the source lines of the LCD panel
100
.
FIG. 3
is a circuit diagram illustrating the gamma reference unit
342
. The gamma reference unit
342
generates a plurality of gamma reference outputs as analog signals having different levels. The gamma reference unit
342
includes a voltage divider that generates a voltage according to the digital signals outputted from the level shifting unit
330
. The voltage divider includes a plurality of resister arrays. A gamma reference output is then transmitted to the buffering unit
360
.
FIG. 4
is a diagram illustrating one channel of the decoding unit
344
.
FIG. 5
is a circuit diagram illustrating one channel of the decoding unit
344
. The decoding unit
344
includes eight serially coupled switch units. The output of the gamma reference unit
342
generally has to pass through the eight serially coupled MOS transistors in order to be transmitted to the buffering unit
360
.
With this configuration,
510
MOS transistors are needed. Because the gamma reference output signals have to pass through the eight switches, the operational speed of the TFT-LCD driver is decreased and the signals become weak. In other words, it takes a long time to drive the signals resulting in decreased operational speed of the driver due to the increased resistance from the number of interconnections. The increased resistance aggravates a phase margin of an operational amplifier and causes a resistance-capacitance (RC) delay so that additional time is required to drive the signals. Accordingly, a configuration capable of reducing the number of switch units is desirable.
FIG. 6
is a circuit diagram illustrating one channel of an existing decoding unit
344
using an improved 4×16 decoder. The 4×16 decoder may be used to solve the above-stated problems. The voltage generated by the voltage divider having the resistor arrays in the gamma reference unit
342
is outputted and passed through just two switch units.
FIG. 7
is a circuit diagram illustrating the 4×16 decoder of FIG.
6
. The 4×16 decoder includes several NAND gates and several inverters. However, in configuring the resistance digital/analog (RDA) converter using the 4×16 decoder, the size of the integrated circuit is considerably increased because the 4×16 decoder occupies a large area in an integrated circuit. Generally, to implement a 4-input NAND gate, three NAND gates and two inverters are required. Each NAND gate comprises two NMOS transistors and resistor, or alternatively four NMOS transistors. Also, the inverter includes CMOS transistors, for example, one PMOS transistor and one NMOS transistor. Accordingly, the 4×6 decoder is costly due to the number of transistors required to implement the 4×6 decoder.
SUMMARY OF THE INVENTION
In accordance with an aspect of the invention, a decoding apparatus is provided which includes: an input for inputting digital data signals; a switch for selecting an output node from among the plurality of output nodes in response to the digital data signals provided from the input; and a precharge circuit for precharging a plurality of output nodes in response to a precharge signal.
In accordance with another aspect of the invention, a resistance array digital/analog converting apparatus is provided which includes: a decoding circuit having a plurality of output nodes, the decoding circuit including: an input for inputting digital data signals; a precharge circuit for precharging the plurality of output units with a first logic value in response to a precharge signal before the plurality of output nodes are enabled by a digital data signal provided from the input; and a first switch for selecting an output node from among the plurality of output nodes in response to the digital signals provided from the input. The resistance array digital/analog converting apparatus further includes: a gamma reference signal generating circuit for generating analog signals having a plurality of different levels; and a second switch for selecting one signal from the analog signals and outputting the selected signal in accordance with signals outputted from the decoding circuit.
In accordance with yet another aspect of the invention a decoding method is provided which includes: precharging a plurality of output nodes with a first logic value; providing a second logic value to an output node from among the plurality of output nodes according to a first inputted digital data signa
Hynix / Semiconductor Inc.
Marshall & Gerstein & Borun LLP
Nguyen John B
Young Brian
LandOfFree
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