Decoder buffer circuit incorporated in semiconductor memory devi

Details Decoder buffer circuit incorporated in semiconductor memory devi Decoder buffer circuit incorporated in semiconductor memory devi

1989-02-21

1990-08-28

Popek, Joseph A.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523008, G11C 700

Patent

active

049531336

ABSTRACT:
For decreasing the number of component transistors, a decoder buffer circuit has a first gate transistor activated on the selection of the two word lines associated thereto for an establishment of a current path, first and second complementary inverter circuits operative to complementarily activate one of the two word lines with a current fed from the current path depending upon the leaest significant bit of a row address signal, and a second gate transistor operative to isolate the two word lines from each other during the operation of the first and second complementary inverter circuits and to ground the two word lines outside the operation, so that the decoder buffer circuit is formed by only six component transistors for complementary activation of the two word lines.

REFERENCES:
patent: 4085460 (1978-04-01), Lodi

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