Decoder buffer circuit for MNOS memory

Details Decoder buffer circuit for MNOS memory Decoder buffer circuit for MNOS memory

1976-04-05

1978-04-18

Hecker, Stuart N.

Static information storage and retrieval

Addressing

307DIG1, 365184, G11C 700

Patent

active

040854604

ABSTRACT:
The decoder buffer is utilized in a memory system for an array of variable threshold MNOS transistor memory cells arranged in word rows. The gate electrodes of the memory transistors comprising each word row is coupled via a word line to the output of a decoder buffer. Inputs to the decoder buffers are provided from address decoder and inverter circuits in response to memory address inputs. FET control circuitry is included for selectively providing operating voltages to the decoder buffers in accordance with the various memory functions performed. Each decoder buffer comprises first, second and third fixed threshold field effect transistors, the first and second transistors being serially connected with respect to each other, forming a junction therebetween which is coupled to the associated one of the memory word lines. The third transistor is connected between the gate of the first transistor and the junction between the first and second transistors, the associated address decoder output line being connected to the gate of the first transistor. The control circuits provide operating voltages selectively to the electrodes of the first and second transistors opposite the junction and to the gate electrode of the third transistor for controlling the buffers in the various modes of the memory.

REFERENCES:
patent: 3747072 (1973-07-01), Lodi et al.
patent: 3772607 (1973-11-01), Luckett et al.
patent: 3971001 (1976-07-01), Lodi

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