Decoder and reproducing unit

Details Decoder and reproducing unit Decoder and reproducing unit

2005-02-22

2005-02-22

Tran, Thai (Department: 2616)

Motion video signal processing for recording or reproducing

Local trick play processing

With randomly accessible medium

C348S423100

Reexamination Certificate

active

06859612

ABSTRACT:
A slow decode control part divides a reference clock generated by a VCXO at a ratio of a slow speed to a normal speed. An STC circuit counts the divided clock. A time for starting decoding by an MPEG video decode part is decided by comparing a DTS included in MPEG data with the count of the STC circuit. A display time determination part determines a timing for outputting decoded data by comparing a PTS included in the MPEG data with the count of the STC circuit. Decoded data temporarily held in a frame buffer is output in response to a signal generated in a determination part on the basis of frame frequency information included in the MPEG data. Thus, slow reproduction is implemented with a high degree of freedom not limited to an integer-fractional speed without requiring a complicated circuit structure.

REFERENCES:
patent: 6078722 (2000-06-01), Kawamura et al.
patent: 6564004 (2003-05-01), Kadono
patent: 6643449 (2003-11-01), Nagata et al.
patent: 6658199 (2003-12-01), Hallberg
patent: 146339 (1999-05-01), None

Affiliated with

Also associated with

Rating

Decoder and reproducing unit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Decoder and reproducing unit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Decoder and reproducing unit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3448459