Decoder and driver for use in a semiconductor memory

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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36518909, 326105, G11C 800

Patent

active

054485274

ABSTRACT:
A decoder formed of multiple circuit blocks each including bipolar transistors Q1 and Q2 having their collectors connected to resistors R1 and R2, respectively, a bipolar transistor Q3 having its collector supplied with a power voltage, and a current source I1 connected commonly to the emitters of Q1-Q3. This circuit configuration permits the decoder and BiCMOS memories using it to operate with a low supply voltage.

REFERENCES:
patent: 4394657 (1983-07-01), Isogai
patent: 5023478 (1991-06-01), Boudon
patent: 5034630 (1991-07-01), Sugiyama
patent: 5252863 (1993-10-01), Hatsuda
The transactions C of the Institute of Electronics, Information and Communication Engineers, of Japan, vol. J70-C, No. 6, pp. 783-790.

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