1974-11-29
1976-09-07
Claffy, Kathleen H.
H04M 150
Patent
active
039795624
ABSTRACT:
An improved decoder is settable to recognize the digits of a preselected code and utilizes two complementary semi-conductor digital counters. Such counters draw very little current from their operating voltage supplies unless and until an energized output line of the counter is connected to a low voltage sink for such current. The first counter is advanced in response to a spacing (interdigit) pulse which follows the transmission of a digit, provided that such a spacing pulse is preceded by a "correct" digit of the preselected code number as received by the second counter. An energized output line of the first counter is connected to that output of the second counter which would be energized if the correct code digit had appeared. If the bilevel voltages of the interconnected lines are in agreement, indicating appearance of a correct code digit, they do not draw current from each other. If the bilevel voltages of the interconnected lines are in disagreement indicating appearance of an incorrect digit, very substantial current is drawn from the first counter. The current flow from the voltage supply of the first counter is monitored by a transistor switching circuit which responds to substantial current flow to order the resetting and clearing of the counters, so that the first counter can only reach its peak count if the required sequence of correct code numbers appears.
REFERENCES:
patent: 3537001 (1970-10-01), Friend
patent: 3760269 (1973-09-01), Beeman
patent: 3790720 (1974-02-01), Schartmann
Claffy Kathleen H.
Popek Joseph A.
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