Decoder

Details Decoder Decoder

1991-01-31

1992-09-15

Gregory, Bernarr E.

Cryptography

Particular algorithmic function encoding

380 49, 364739, 364744, 364746, 3647461, 364771, G06F 750

Patent

active

051484803

ABSTRACT:
A decoder having a plurality of outputs (R.sub.0 -Rn) each associated with a particular output valve is arranged to add together two binary numbers (A, B) and to select one of the outputs in dependence on the result of the sum. The decoder comprises a plurality of logic circuits each arranged to receive respective bits of both first and second binary numbers to be added together. The logic circuits are arranged to provide, for each output value, a respective result in dependence on the logic states of respective bits of binary numbers representing that particular output value of the decoder. The logic means determines when a predetermined condition is satisfied by the results of the logic circuits associated with an output value of the decoder, whereby that output value is selected.

REFERENCES:
patent: 3372377 (1968-03-01), Cohn et al.
patent: 3541314 (1970-11-01), Webb
patent: 3604909 (1971-09-01), Vogel et al.
patent: 3694642 (1972-09-01), Grannis
patent: 3748649 (1973-07-01), McEowen et al.
patent: 4187549 (1980-02-01), Bond et al.
patent: 4810995 (1989-03-01), Kondou et al.
patent: 4873660 (1989-10-01), Nishiyama et al.
patent: 4918638 (1990-04-01), Matsumoto
"Evaluating A+B=K Conditions in Constant Time" by J. Cortadella and J. M. Llaberia. ISCAS (1988).

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