Decoded instruction cache architecture with each instruction fie

Details Decoded instruction cache architecture with each instruction fie Decoded instruction cache architecture with each instruction fie

1993-12-22

1995-08-15

Treat, William M.

Boots, shoes, and leggings

395800, 36423223, 3642318, 36424342, 364DIG1, G06F 930

Patent

active

054427606

ABSTRACT:
A general purpose computer system is equipped with apparatus for enabling a processor to provide efficient execution of multiple instructions per clock cycle. The major feature is a decoded instruction cache with multiple instructions per cache line. During run time cache hits, the decode logic fills the cache line with instructions up to its limit. During run time cache misses, the cache line enables the processor to dispatch multiple instructions during one clock cycle. Hereby is achieved high performance with a simple, but still powerful, decode and dispatch logic.
An important feature of the instruction cache is that it holds the target addresses for the next instructions. No separate address logic is needed to proceed in the program execution during cache hits. A conditional branch holds its alternative target address in a separate field. This enables the processor, to a large degree, to be independent of the conditional branch bottleneck.

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