Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-05-10
2001-09-11
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S063000, C365S230060, C365S230090, C365S239000
Reexamination Certificate
active
06288937
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates to programmable logic devices, and in particular, to the interconnects or routing pools for such devices.
2. Description of Related Art
Integrated circuits (ICs) can be designed to implement and carry out desired functions for various applications and needs. One such IC is the application specific integrated circuit or ASIC, which are designed to carry out specific applications. However, ASICs can only be used for the applications they were desired for. As circuitry and functions become more and more complex, requiring very specific functions for the IC to perform, designing, testing, and manufacturing ASICs for very narrow uses can increase the cost per ASIC and make the ASIC cost prohibitive.
Programmable logic devices (PLDs) can implement a variety of functions using a single semiconductor chip.
FIG. 1
shows a generalized PLD
100
which includes an interconnect or generic routing pool (GRP)
110
, a programmable array logic (PAL)
120
, and a generic logic blocks (GLBs)
130
. GRP
110
is a global interconnect circuit or matrix for selecting desired signals to be applied to PAL
120
, i.e., for connecting desired terms to PAL
120
. The signals can be selected from external input/output (I/O) pins, output terminals of GLBs
130
, or other suitable signal sources. The total number of signals or terms input to GRP
110
can be hundreds or even thousands. The desired signals are then selected by GRP
110
and routed to input terminals of PAL
120
, which is a programmable array of AND gates. After performing desired AND functions on the selected terms, the resulting product terms are input to GLBs
130
. GLBs
130
, also known as macrocells, contain a programmable array of OR gates for performing OR functions on the input product terms, i.e., selective summing of the product terms. In addition to OR gates, a GLB can also include other logic gates, such as exclusive OR (XOR) gates, registers, I/O cells, etc. The output signals from GLBs
130
can then be used for the desired application or can be fed back into GRP
110
for further processing.
The programmable arrays or matrices within GRP
110
, PAL
120
, and/or GLBs
130
are programmed according to the specification provided by the circuit designer for implementing the desired function. Programming typically involves either selectively breaking or maintaining electrical connections between GRP input signals, the AND gates, and the OR gates.
FIG. 2
shows an interconnection matrix
200
, which is a portion of GRP
110
for selectively making the desired connections from the input terminals to the output terminals of GRP
110
. Matrix
110
has four input terminals
201
-
204
coupled to four corresponding columns of signal lines and three output terminals
211
-
213
coupled to three corresponding rows of signal lines. Note that the use of “rows” and “columns” is arbitrary, simply designating directions of the signal lines. Also, it should be noted that any number of input terminals and output terminals are possible, with the number of output terminals typically more than or equal to the number of input terminals.
The rows and columns are approximately orthogonal to each other, with a pass transistor coupled at the intersection of each row and column signal line. Each pass transistor
221
-
232
acts as a switch to either connect or disconnect the signal at an input terminal to the corresponding output terminal. Pass transistors
221
-
232
are shown as N-type transistors, although other types are also suitable. The drain of each pass transistor is coupled to a corresponding column signal line and the source of each pass transistor is coupled to a corresponding row signal line. The control gate of each pass transistor
221
-
232
is coupled to the output terminal of an associated programmable cell
221
A-
232
A. Programmable cells
221
A-
232
A, which typically include non-volatile memory cell(s), apply different voltage levels to the control gates of the pass transistors, based on user-supplied input signals to the programmable cells. In general, the programmable cells can be any circuit or device capable of holding and outputting a state and its complement in response to external inputs.
Connections from signals on the input terminals to an output terminal are made by turning on the desired pass transistor, where a “high” voltage to the control gate turns on a pass transistor and a “low” voltage to the control gate turns off a pass transistor. For example, if pass transistors
223
,
225
, and
232
are on (programmable cells
223
A,
225
A, and
232
A apply “high” voltages), current flows through pass transistors
223
,
225
, and
232
, thereby pulling voltages at output terminals
211
-
213
up to the voltages at input terminals
203
,
201
, and
204
, respectively. The voltages at the input terminals can be from I/O pins, feedback from the GLBS, etc. The signals at output terminals
211
-
213
are then input to PAL
120
for ANDing.
As seen from
FIG. 2
, a GRP requires twelve programmable cells and pass transistors or switches in order to provide complete connectivity between the four input terminals and the three output terminals. However, as semiconductor technology continues to advance and functions become more complex, PLDs are needed to perform functions requiring larger numbers of inputs and input combinations, which necessitates larger sized routing devices. A typical PLD currently in use selects 16 out of 256 signals for transmission to a PAL for the ANDing function (e.g., a 2128 device from a 2K family of devices, such as from Lattice Semiconductor, Corp. of Hillsboro, Oreg.). Thus, in order to provide complete connectivity, 4,096 (16*256) programmable cells are required in the GRP.
However, implementation of a PLD having a GRP with over four thousand programmable cells and switches or interconnects is impractical. Thus, a GRP can be designed where the 256 input signals are partitioned into 16 groups of 16 signals. One signal is selected from each of the 16 groups and input into an AND array. Thus, 16 out of the 256 input signals are selected for ANDing. This reduces the number of programmable cells and interconnects from 4096 to 256 (16*16) for a 16-fold reduction. However, this reduction comes with the price of decreased connectivity because the 256 input signals can no longer be connected in any combination to 16 outputs.
FIG. 3
shows a 1×16 interconnection matrix
300
for selecting one of 16 signals. Sixteen matrices
300
allow 16 signals to be selected from 256 signals. Matrix
300
includes 16 pass transistors
301
-
316
coupled to 16 programmable cells
301
A-
316
A, respectively, with each pass transistor coupled to a column signal line and all 16 pass transistors coupled to one row signal line, similar in operation to that of matrix
200
of FIG.
2
. Matrix
300
has the 16 column signal lines coupled to 16 input terminals and the row signal line coupled to one output terminal. The output terminal is coupled to one input of a 16-input AND array
360
. Thus, using this configuration, 16 of matrices
300
, utilizing a total of 256 programmable cells, can be used to select 16 of 256 signals for transmission to the AND array. However, this configuration does not allow two or more signals from a group of 16 signals to be selected for inputting to the AND array. For example, if programmable cell
302
A turns on pass transistor
302
, thereby placing the signal at the associated input terminal
322
on the row signal line, the other 15 signals of the group at input terminals
321
and
323
-
336
cannot be selected.
FIG. 4
is another interconnection matrix
400
that allows greater selectivity of input signals by using two 1×32 matrices
400
A and
400
B coupled to the same group of 32 input signals. Matrices
400
A and
400
B each are a 1×32 matrix for selecting one of 32 input signals. Matrix
400
A, which is the same as matrix
400
B, includes 32 pass transistors
401
-
432
coupled to 32 programmable cells
401
A-
Chen Tom
Lattice Semiconductor Corporation
Nelms David
Skjerven Morrill & MacPherson LLP
Yoha Connie C.
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