Decoded counter with error check and self-correction

Details Decoded counter with error check and self-correction Decoded counter with error check and self-correction

1994-06-15

1996-06-11

Wambach, Margaret Rose

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Identifying or correcting improper counter operation

377 31, 377 46, 377 54, 377 80, H03K 2140, H03K 2354

Patent

active

055263909

ABSTRACT:
A decoded counter employing a shift register and a zero-detect circuit has the ability of returning to a correct state within a limited number of clock cycles if an invalid state is accidentally assumed by the counter. One of the flip-flops is provided with synchronous set while all the other flip-flops of the shift register are provided with synchronous reset. The output of the last flip-flop of the register drives a single set-reset line common to all the flip-flops and the pull-up line of the zero-detect circuit is connected to the input of the first flip-flop of the register. Optionally, one of the flip-flops may be provided with asynchronous set and the others with an asynchronous reset, for initializing the counter in a certain state through a single clear-load line.

REFERENCES:
patent: 3639740 (1972-02-01), Escoffier et al.
patent: 5373542 (1994-12-01), Sunouchi
Patent Abstracts of Japan, vol. 16, No. 199 (P-1351) May 13 1992 & JP-A-40 30 398 (Matsushita Electric Ind Co Ltd) Feb. 3, 1992 *abstract*.
Patent Abstracts of Japan, vo. 16, No. 423 (E-1260) Sep. 7, 1992 & JP-A-41 45 721 (NEC IC Microcomput Syst Ltd) May 19, 1992 *abstract*.
IBM Technical Disclosure Bulletin, vol. 25, No. 3A, Aug. 1982 pp. 1073-1074, G. D. Miller et al.: "Johnson Counter with Error Correction" *the whole document*.

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