Decode path gated low active power SRAM

Details Decode path gated low active power SRAM Decode path gated low active power SRAM

2005-04-05

2005-04-05

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S233100, C365S239000

Reexamination Certificate

active

06876595

ABSTRACT:
Circuits and methods for controlling data access operations in memory devices such as SRAM (static random access memory) devices. The circuits and methods provide timing and control for memory access operations by propagating a control pulse along a decode path from which a sequence of control pulses are generated at points in the decode path to synchronize activation of wordlines and sense amplifiers and precharge/equalization of bit lines. Preferably, an address gated pulse schema is implemented to synchronize and restrict switching activity spatially and temporally to only regions of a memory array that are being accessed, and for limited periods of time just sufficient to generate signals for read or write operations. Advantageously, the circuits and methods enable SRAM cell delays to track CMOS gate delays more closely at low voltages and reduce switching power by restricting switching transitions only to the regions of memory that are accessed.

REFERENCES:
patent: 5936977 (1999-08-01), Churchill et al.
patent: 6069839 (2000-05-01), Pancholy et al.
patent: 6151266 (2000-11-01), Henkels et al.

Affiliated with

Also associated with

Rating

Decode path gated low active power SRAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Decode path gated low active power SRAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Decode path gated low active power SRAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3412861