Decode circuitry for bipolar random access memory

Details Decode circuitry for bipolar random access memory Decode circuitry for bipolar random access memory

1975-05-02

1977-05-31

Yusko, Donald J.

Communications: electrical

Digital comparator systems

340173R, 307237, G11C 800, H03K 520, H04Q 900

Patent

active

040272850

ABSTRACT:
An N-bit binary address decoder suitable for use in an emitter-coupled logic bipolar random access memory (RAM) is provided. Each of the N address input signals is applied to an input terminal and is level shifted and applied to the input node of an emitter-coupled logic inverter. The outputs of the emitter-coupled logic inverter are the collectors of the emitter-coupled transistors on which complementary output signals representative of the corresponding binary address input signal are produced. The complementary output signals generated by the N inverters are connected to 2.sup.N AND gates to form the possible 2.sup.N minterm combinations. Each of the AND gates includes a load resistor coupled to a power supply and N Schottky diodes having their anodes coupled to the load resistor and their cathodes coupled to the corresponding address inverter output terminals. The anodes of the input diodes of each AND gate are also connected to the base of a transistor, the emitter of which produces the signal representing the corresponding minterm function generated by that AND gate.

REFERENCES:
patent: 3651344 (1972-03-01), O'Shea
patent: 3721964 (1973-03-01), Barrett et al.
patent: 3737859 (1973-06-01), Kadow
patent: 3742250 (1973-06-01), Kan
patent: 3806880 (1974-04-01), Spence
patent: 3824580 (1974-07-01), Bringol

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