Decode circuitry and a display device using the same

Coded data generation or conversion – Digital code to digital code converters – To or from multi-level codes

Reexamination Certificate

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Details

C341S050000

Reexamination Certificate

active

11376136

ABSTRACT:
Multi-bit input data is divided into at least a first bit group and a second bit group, and each of first sub-decode circuits selects one selection target signal/voltage from selection target signal/voltage group in accordance with the first bit group. Then, one signal/voltage is selected according to the second bit group from the signals/voltages selected by the first sub-decode circuits, and is transmitted to an output signal line. Each of second sub-decode circuits is formed of a single train of series switches, and only one of the switch train is made conductive to transmit a finally selected signal/voltage to the output signal line.

REFERENCES:
patent: 6072410 (2000-06-01), Kim
patent: 2000-66642 (2000-03-01), None
patent: 2000-183747 (2000-06-01), None
patent: 2000-242209 (2000-09-01), None
patent: 2001-133754 (2001-05-01), None
patent: 2003-29687 (2003-01-01), None
patent: 2003-241716 (2003-08-01), None

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