Decode circuit for a semiconductor memory device

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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Details

36523003, 36518511, G11C 1700

Patent

active

054775000

ABSTRACT:
A semiconductor memory device, comprising: first row lines; selecting transistors driven by the first row lines; second row lines; memory cells driven by the second row lines and connected in series with the selecting transistors; first selecting means for selecting the first row lines; second selecting means for selecting the second row lines; column lines connected to the selecting transistors; data detecting means connected to the column lines, for detecting data stored in the memory cells; first switching means connected between the first selecting means and the second row lines, for selecting the second row lines in response to the second selecting means; and second switching means connected between a potential supply terminal for supplying a predetermined potential and the second row lines, for selecting the second row lines in response to the second selecting means.

REFERENCES:
patent: 5008856 (1991-04-01), Iwahashi
patent: 5043942 (1991-08-01), Iwata et al.
patent: 5297084 (1994-03-01), Ban

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