Decode and dispatch of multi-issue and multiple width...

Details Decode and dispatch of multi-issue and multiple width... Decode and dispatch of multi-issue and multiple width...

2006-06-27

2006-06-27

Tsai, Henry W. H. (Department: 2181)

Electrical computers and digital processing systems: processing

Instruction decoding

C712S210000

Reexamination Certificate

active

07069420

ABSTRACT:
In one particular embodiment, a processor receives and processes a plurality of instruction from a single instruction register. The processor loads the plurality of instructions into a single register and determines the number and size of instructions while the instructions are in the register. Each of the plurality of instructions is then simultaneously presented to the decoder. The decoder then decodes a first of the plurality of instructions and determines whether any additional instructions are present.

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