Pulse or digital communications – Repeaters – Testing
Patent
1988-08-31
1990-03-27
Griffin, Robert L.
Pulse or digital communications
Repeaters
Testing
375120, 328109, 307514, H04L 2549
Patent
active
049127268
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a decision timing control circuit provided in the receiving side of the radio data transmission system utilizing the multi-level amplitude modulation method.
2. Description of the Related Art
In the radio data transmission system utilizing the multi-level amplitude modulation, for instance, the 64-level quadrature amplitude modulation (QAM), binary transmission data in the sending side is distributed to 3 bits for I channel and 3 bits for Q channel. The 3 bits of respective channels are subjected to digital-to analog D/A conversion in the timing of a predetermined clock which converts these signals converted to 8-level signals both in the I channel and Q channel. The 8-level signals of I and Q channels are respectively transmitted after the quadrature amplitude modulation.
A constitution of the receiving side is indicated in FIG. 1. A demodulator 10 inputs a receiving signal S.sub.in from a receiver (not illustrated) and outputs the 8-level signals S.sub.ai, S.sub.aq of I and Q channels. The 8-level signals S.sub.ai, S.sub.aq of both I and Q channels are respectively input to data recovery circuits 20, 30 of I and Q channels and the I channel signal is also input to a bit timing recovery circuit (BTR) 40. The bit timing recovery circuit 40 rectifies the 8-level signal S.sub.ai of I channel with a full-wave rectifier 41 to generate a clock element. The full-wave rectified signal is then input to a phase comparator 43 together with an output of a voltage controlled oscillator (VCO) 42. A phase difference signal output from the phase comparator 43 is applied as a control voltage to VCO 42 through a low-pass filter 44. Thereby, VCO 42 outputs the clock signal CLK which is synchronized with the 8-level signal S.sub.ai of I channel.
Meanwhile, the data recovery circuit 20 of I channel inputs the 8-level signal S.sub.ai of I channel to the A/D converter 22 provided as a decision circuit through an equalizer 21. The A/D converter 22 inputs the clock CLK sent from the bit timing recovery circuit 40 through a variable phase shifter 23, decides the 8-level signal S.sub.ai of I channel input in the timing of clock CLK and converts it into a binary digital signal, and outputs the 1 bit lower than the upper 3 bits as the decision error signal .epsilon. with such upper 3 bits used as the decision data S.sub.d. Moreover, the data recovery circuit 30 of Q channel has the structure similar to that of the data recovery circuit 20 of I channel.
For the radio communication system, it is necessary to limit the frequency band of the sending; therefore, a filter is used in the sending side. Accordingly, the 8-level signal demodulated in the receiving side has the gentle waveform in place of the rectangular waveform. As a result, the 8-level signal demodulated has the eye pattern indicated in FIG. 2 which has a eye aperture A that is rather narrow.
As the decision timing deviates from the center of such aperture A, the error rate becomes worse. Therefore, the phase of recovered clock is adjusted manually with the variable phase shifter and it is fixed when decisions are carried out at the optimum decision timing T.sub.s.
However, here lies a problem in that it is likely that as the clock phase deviates, even after it is once fixed, from the optimum decision timing due to temperature change or voltage variation and it is difficult to quickly match the clock phase and optimum decision timing during the pulling-in period in the initial stage of data transmission or when intersymbol interference due to the fading sometimes appearing increases.
In addition, there is a problem that the demodulated multi-level signal S.sub.ai (S.sub.aq) is disturbed during pulling-in period or when intersymbol interference increases, lacks the number of credible signal points required to control synchronization between clock phase and optimum decision timing. Hence, a longer time is required until the end of control for matching. Furthermore, it is also a problem that
REFERENCES:
patent: 3755736 (1973-08-01), Kaneko et al.
patent: 4002982 (1977-01-01), Catania
patent: 4351061 (1982-09-01), Hedin et al.
patent: 4376309 (1983-03-01), Fenderson et al.
patent: 4435825 (1984-03-01), Tomooka
patent: 4635277 (1987-01-01), Blake et al.
patent: 4661801 (1987-04-01), Chen et al.
International Search Report for PCT/JP88/00013; Japanese Patent Office, 3/28/88.
Aono Yoshihito
Iwamatsu Takanori
Minowa Morihiko
Takenaka Sadao
Chin Stephen
Fujitsu Limited
Griffin Robert L.
LandOfFree
Decision timing control circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Decision timing control circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Decision timing control circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1656678