Decimetor circuit of simple construction and high speed operatio

Details Decimetor circuit of simple construction and high speed operatio Decimetor circuit of simple construction and high speed operatio

1991-01-14

1992-04-28

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Counter controlled counter

377 49, 377 56, H03K 2110

Patent

active

051093952

ABSTRACT:
A decimetor circuit is constructed to execute an FIR filtering of "n" taps for input data sampled with a sampling frequency "f" and then to resample an output of the FIR filter at a frequency of "f/m". A first counter of a "divided-by-n/m" type is driven with a clock having a frequency of "n/m" of the sampling frequency "f" and selectively operates either in a first counting condition in which the first counter is incremented by one count with each clock pulse of the clock or in a second counting condition in which the first counter is incremented by two counts with each clock pulse of the clock. A second counter of a "divided-by-n" type is driven with the clock and incremented by one count with each clock pulse of the clock. A first decoder is coupled to the second counter for decoding a content of the second counter so as to bring the first counter either into the first counting condition or into the second counting condition. An address generation circuit is connected to the first and second counters for generating an address obtained by adding a "m
" of the content of the second counter with "m" times of a content of the first counter. A coefficient memory receives the address for outputting a coefficient designated by the received address, and a multiplier multiplies the input data by the received coefficient. An adder circuit has a first input connected to receive the result of multiplication, and a second input connected to a "n/m"-stage shift register which receives an output of the adder circuit and is shifted by the clock so as to output a shifted data from a final stage of the "n/m"-stage shift register. A latch circuit periodically latch the output of the adder circuit.

REFERENCES:
patent: 4199719 (1980-04-01), Grob
patent: 4741002 (1988-04-01), Dougherty
patent: 4809221 (1989-02-01), Magliocco et al.

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