Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-07-27
2001-01-09
Ngo, Chuong Dinh (Department: 2787)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06173302
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a decimation method, the transfer function of which substantially corresponds to the transfer function of a CIC decimation filter, and in which a signal including digital samples is decimated by coefficient M.
The invention also relates to a decimation filter, the transfer function of which substantially corresponds to the transfer function of a CIC decimation filter, and which is arranged to decimate a signal including digital samples by coefficient M.
BACKGROUND OF THE INVENTION
Digital signal processing comprises several applications in which sampling should be changeable. In decimation, the sampling period is increased, whereby the sampling frequency decreases. This allows to reduce the number of data points processed or stored in the memory per a time unit.
In a receiver of the radio system, for example, an analogue/digital conversion is carried out on a pass band signal by using a high sampling frequency. After the A/D conversion the frequency of the pass-band signal is decreased to the level of the base band, but the sampling frequency still remains high. Excessive sampling can be reduced by using a decimation filter, which also improves the signal-to-noise ratio.
A CIC decimation filter (Cascaded Integrator-Comb), for example, is a conventional decimation filter, which reduces sampling of a signal by a high coefficient. The CIC filter comprises a number of integrators in serial form, a decimation part and a number of successive comb filters. Such a filter can be implemented e.g. by using adder/subtractor structures, and thus it can be used at high frequencies. With respect to a more detailed description of the solution a reference is made to An Economical Class of Digital Filters for Decimation and Interpolation, E. B. Hogenauer.
A problem associated with the decimation filter employing integrators is that the long-term expected value of input data has to be zero, i.e. the data must not contain any DC offset. Even a minor DC offset in the input data causes overloading of integrators, and a functional error in the decimation filter. In order to avoid the DC offset, twos complement arithmetic or the like is used, comprising deducing positive and negative numbers from one another by means of a simple bit exchange. The problem can also be diminished by increasing the word length of the decimation filter, but as such this does not eliminate the problem.
BRIEF DESCRIPTION OF THE INVENTION
An object of the present invention is to provide decimation filtering and a decimation filter which realize the transfer function of a CIC decimation filter, but which function without becoming overloaded even when the expected value of input data deviates from zero.
This is achieved with the method described in the introduction. The method is characterized in that at least main processing is performed on the signal to be decimated, the main processing comprising the steps of performing M-tap FIR filtering N times in sequence, decimating by coefficient M and comb-filtering the signal N−1 times.
The decimation filter of the invention is characterized in that it at least comprises a main branch, which comprises decimation means, which decimate by coefficient M, N M-tap FIR filters in sequence before the decimation means of the main branch, and N−1 combinations of a comb filter and an adder in sequence after the main branch of the decimation means.
The decimation filter of the invention is also characterized in that it at least comprises a main branch, which comprises decimation means, N M-tap FIR filters before the decimation means of the main branch, which decimate by coefficient M; and if the number N of M-tap FIR filters is more than one, the decimation filter is arranged to take into account N−1 sample cycles M preceding the incoming sample cycle M, and thus, in addition to the main branch, the decimation filter comprises selection means; memory; shift means; adder/subtractor means and control means; N−1 side branches, the divergence point of which is operationally connected between each of two FIR filters before the decimation means of the main branch, and their other end is operationally connected to the selection means, the side branches comprising decimation means for decimating the signal coming to the side branch by coefficient M; delay means for delaying the decimated signal by one M sample cycle; additional branches comprising delay means for delaying the signal by one sample cycle M, the divergence point of the additional branches being operationally connected after each delay means in the side branch or additional branch, and their other end being operationally connected to the selection means; the selection means of the decimation filter are arranged to select one signal at a time from the main branch, side branch or additional branch for an arithmetic shift operation for the shift means; the shift means of the decimation filter are arranged to perform necessary arithmetic shift on each signal of the main branch, side branch or additional branch; the adder/subtractor means of the decimation filter are arranged to calculate the difference of signals according to comb-filtering and to add the signal of each side branch or additional branch to the result provided; the memory of the decimation filter is arranged to store the results provided for the signals of each main branch, side branch and additional branch and the sums of the results; the control means of the decimation filter are arranged to control the function of the decimation filter so that the decimation filter substantially provides the transfer function of the CIC decimation filter.
The method of the invention provides several significant advantages. Overload situations due to the DC offset of the decimation filter can be avoided and hence the filter will function more reliably in all circumstances. Furthermore, arithmetic to be used in decimation can be selected freely.
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Apr. 1981, Hogenauer,IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. ASSP-29, No. 2, “An Economical Class of Digital Filters for Decimation and Interpolation”, pp. 155-162.
Altera Law Group LLC
Ngo Chuong Dinh
Nokia Telecommunications Oy
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