Decimation filter in a sigma-delta analog-to-digtal converter

Details Decimation filter in a sigma-delta analog-to-digtal converter Decimation filter in a sigma-delta analog-to-digtal converter

1992-05-04

1993-06-15

Hoff, Marc S.

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

3647241, H03M 302

Patent

active

052203271

ABSTRACT:
A decimation filter for converting a train of sigma-delta pulses S(i) in synchronism with a sigma-delta clock (fs) into a train of PCM samples which includes counters (321, 331, 341) driven by the sigma-delta clock (fs) and which is continuously incremented by one during N sigma-delta clock pulses, then decremented by two during N following sigma-delta clock pulses and then incremented again by one during N following sigma-delta clock pulses in order to provide a sequence of incrementation parameter DELTA(n). The decimation filter further includes storages (320, 330, 340) for storing the value of the coefficient C(n) corresponding to the decimation filter transfer function, and incrementers (327, 337, 347) driven by the sigma-delta clock fs for incrementing the storages with the incrementation parameter DELTA(n). Finally, the decimation filter includes computers (323, 333, 343, 327, 337, 347) for deriving from the contents C(n) of said storages and from the train of input sigma-delta samples S(i+n) one Pulse Code Modulation (PCM) sample every 3.times.N input sigma-delta samples according to the formula: ##EQU1##

REFERENCES:
patent: 4775851 (1988-10-01), Borth
patent: 4972360 (1990-11-01), Cukier et al.
patent: 5027306 (1991-06-01), Dattorro et al.
patent: 5126961 (1992-06-01), Garverick
ICASSP 85, IEEE International Conference on Acoustics, Speech, and Signal Processing, Mar. 26-29, 1985, IEEE New York US, pp. 36.2.1-36.2.4; Hanafy Meleis et al: "A Novel Architecture Design for VLSI Implementation or and FIR Decimation Filter".
IEEE Journal on Selected Areas in Communication, vol. 6, No. 3, Apr. 1988, New York, pp. 520-526; Vladimir Friedman et al: "A Bit-Slice Architecture for Sigma-Delta Analog-to-Digital Converters".

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