Decimation filter for a sigma-delta converter and data circuit t

Details Decimation filter for a sigma-delta converter and data circuit t Decimation filter for a sigma-delta converter and data circuit t

1992-05-04

1994-07-12

Chin, Stephen

Pulse or digital communications

Repeaters

Testing

375113, 36472404, 3647241, 341143, H04B 1406, H04L 706

Patent

active

053295536

ABSTRACT:
A decimation filter for converting a received train of sigma-delta pulses in synchronism with a sigma-delta clock (fs) into a train of Pulse Code Modulation (PCM) samples having a PCM clock in accordance with the formula ##EQU1## includes a computer for computing one PCM sample from a sequence of sigma-delta samples in synchronism with the PCM clock and also a comparison circuit for determining whether phase correction of the PCM clock is necessary to lock the generation of the PCM samples on the sigma-delta clock extracted from the received sigma-delta signal, the decimation filter including shifters which shift the computation process at least one sigma-delta clock pulse in order to provide phase control in the generation of the PCM samples.

REFERENCES:
patent: 4937577 (1990-06-01), Rich et al.
patent: 5055843 (1991-10-01), Ferguson, Jr. et al.
patent: 5157395 (1992-10-01), Del Signore et al.
patent: 5191547 (1993-03-01), Kawamoto et al.
"PCM codec with One-Chip Digital Filters" by L. Van De Meeberg and T. G. Janssen, IEEE, 1980.

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