Decimation filter for a sigma-delta converter and A/D converter

Details Decimation filter for a sigma-delta converter and A/D converter Decimation filter for a sigma-delta converter and A/D converter

1992-11-23

1995-10-24

Chin, Stephen

Pulse or digital communications

Pulse code modulation

Correcting or reducing quantizing errors

375254, 341143, 36472404, 3647241, H04B 1404

Patent

active

054616417

ABSTRACT:
A Decimation filter for converting a train of sigma-delta pulses S(i) in synchronism with a sigma-delta clock (fs) into a train of Pulse Coded Modulation (PCM) samples in accordance with the formula ##EQU1## where Cn is the sequence of the coefficients of the decimation filter which corresponds to a determined decimation factor, and the PCM samples being processed by a Digital Signal Processor (DSP). The decimation filter includes a device for storing a digital value representative of the DC component introduced during the sigma-delta coding process, with the digital value being computing by the DSP processor during an initialization phase. The decimation filter further includes a device operating after the latter initialization phase for subtracting the stored digital value from each of the PCM samples so that the resulting sequence of PCM samples appears free of any DC component introduced during the sigma-delta coding. This accurate DC component suppression is achieved without necessitating the use of additional digital signal processor resources from the processor. Preferably, the decimation filter comprises a device for detecting a saturation occurring in the computing of the PCM sample, and responsive to the saturation detection, for transmitting a predetermined PCM sample to the DSP processor.

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ICASSP 85, IEEE Int. Conf. on Acoustics, Speech & Signal Processing; Mar. 1985; pp. 36.2.1-36.2.4; Hanafy Meleis et al.

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