Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2006-06-27
2006-06-27
Malzahn, D. H. (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
07069285
ABSTRACT:
Folding noises into signal bands are reduced and steeper cutoff characteristics are achieved without any increase in the scale of the circuit of a decimation filter attributable to the order of the filter coefficients and the bit precision of the same.Smaller attenuations are achieved in regions that do not contribute to folding noises, and filter coefficients are used to primarily attenuate signal components in regions contributing to folding noises and having a certain band width located about frequencies that are integral multiples of a decimated sampling frequency of 8 fs, thereby reducing folding noises compared to the prior art. Attenuations smaller than those in the prior art are achieved in other regions that do not contribute to folding noises to allow the filter coefficients to be used to make cutoff characteristics steeper accordingly, thereby achieving steeper cutoff characteristics while keeping folding noises at the level of the prior art.
REFERENCES:
patent: 6750793 (2004-06-01), Takeda
patent: 6834292 (2004-12-01), Jiang et al.
Kawanishi Hiroyuki
Toyama Akira
Jordan and Hamburg LLP
Malzahn D. H.
Nippon Precision Circuits Inc.
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