Decimation circuit employing multiple memory data shifting secti

Details Decimation circuit employing multiple memory data shifting secti Decimation circuit employing multiple memory data shifting secti

1991-07-01

1993-04-27

Mai, Tan V.

Boots, shoes, and leggings

G06F 1531

Patent

active

052068218

ABSTRACT:
A decimating memory includes a memory having addressable memory locations. The memory forms a plurality of registers, each of the registers including at least one addressable memory location. The plurality of registers form a forward shifting data section and a reverse shifting data section. A first decoder operates the registers in the forward shifting data section and all but a first of the registers in the reverse shifting data section as first in first out registers via read and write addressing of the addressable memory locations to input and output data samples. The read and write addressing of the addressable memory locations is offset with respect to one another to provide a decimation factor. A paintbrush decoder operates the first register in the reverse shifting data section as a last in first out register for reverse sequencing data samples within blocks of data samples received from the forward shifting data section. Each of the registers in the forward shifting and reverse shifting data sections provide an output. An arithmetic logic unit section operates on the outputs and provides a decimating memory output.

REFERENCES:
patent: 4489393 (1984-12-01), Kawahara et al.
patent: 4972356 (1990-11-01), Williams
patent: 5126961 (1992-06-01), Garverick
patent: 5148384 (1992-09-01), Ikegaya et al.

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