Decimating down converter and related methods

Coded data generation or conversion – Digital code to digital code converters – Data rate conversion

Reexamination Certificate

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C341S059000

Reexamination Certificate

active

11402086

ABSTRACT:
A system of downconverting an intermediate frequency (IF) phase or frequency modulated signal to a digital baseband includes an N bit shift register circuit that receives a binary input as a 1-bit input sample data stream of an IF signal. A decimation circuit includes a memory and receives data from the N bit shift register circuit and stores N 1-bit binary samples as address bits and performs decimation, downconversion and filtering by accessing memory values at a predetermined rate.

REFERENCES:
patent: 4376933 (1983-03-01), Saran et al.
patent: 5023617 (1991-06-01), Deering
patent: 5023821 (1991-06-01), Argintaru et al.
patent: 5369606 (1994-11-01), Hessel
patent: 5375146 (1994-12-01), Chalmers
patent: 5923273 (1999-07-01), Pastorello
patent: 2004/0208264 (2004-10-01), Norris et al.

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