Decimal multiplier device and method therefor

Details Decimal multiplier device and method therefor Decimal multiplier device and method therefor

1984-12-27

1988-05-17

Harkcom, Gary V.

Boots, shoes, and leggings

364759, G06F 752

Patent

active

047455691

ABSTRACT:
A decimal multiplier device including a register A storing the multiplier, a register B storing the multiplicand, a shifter for outputting the output of the register A as it is or after having been shifted, based on a first signal, a gate for outputting the output of the register B or "0", based on a second signal, an adder/subtractor for adding the output of the shifter and that of the gate and storing the result thus obtained in the register A, and a decoder for receiving the value of a selected digit of the content of the register A and controlling the gate and the shifter by generating the first signal and the second signal based on the received value so that the multiplicand B is added n times, n corresponding to the received value, to the content of the register A or substracted (10-n) times therefrom. The register A, the shifter and the adder/subtractor form a single loop. Decimal multiplication is performed by controlling the shifter, when signals pass through the loop repeatedly.

REFERENCES:
patent: 3293420 (1966-12-01), Pitkowsky et al.
patent: 3500026 (1970-03-01), Pokorny
patent: 4543641 (1985-09-01), Fukuta et al.
patent: 4677583 (1987-06-01), Ohtsuki et al.
Angiulli et al., High Performance Two-Cycle Loop Decimal Multiply Algorithm, IBM Technical Disclosure Bulletin, vol. 24, No. 4, Sep. 1981, pp. 1845-1849.

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