Decibel adjustment device with shift amount control circuit

Details Decibel adjustment device with shift amount control circuit Decibel adjustment device with shift amount control circuit

2000-06-26

2004-01-06

Ngo, Chuong Dinh (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06675186

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a decibel level adjustment device for calculating an output signal that is a decibel multiple of an input signal.
2. Description of the Related Art
In electronics, dB (decibels) are used as the unit for various characteristics (such as signal gain, S/N, noise figure, isolation, and acoustic signal level) that indicate the performance of elements or circuits. Unlike electrical units such as voltage (V), current (A), resistance (&OHgr;), power (W), this unit expresses ratios such as voltage to voltage, current to current, and power to power in terms of logarithms. Since values expressed in dB take the logarithms of antilogarithms, such expression is equivalent to compressing large numbers and expanding small numbers. As a result, even extremely large values (antilogarithms) can be expressed by numbers (dB) having few digits. Expressing electrical characteristics by dB has many advantages when dealing with signals in electronic circuits.
Examples of control by dB are numerous, and include, in particular, digital control by dB of signal levels used in analog wireless and cable communication apparatus, volume control in acoustic devices, and in signals used in, for example, devices for amusement (such as sound effects in games).
In a multiplier that operates to the sixth decimal bit with D as the input signal (data) and decibel multiplier M as the multiplier (in the direction of decrease), if the decibel multiplier M is represented as:
M
=0
.A
1
A
2
A
3
A
4
A
5
A
6
(
A
1
-A
6
being 1 or 0)
then, in decimal notation:
m=A
1
/2
+A
2
/4
+A
3
/8
+A
4
/16
+A
5
/32
+A
6
/64
The multiplication is actually D×each bit of M, and the circuit therefore has a construction such as shown in FIG.
1
. The input data are multiplied by the value of the A
1
bit at multiplier
311
. The result is added at adder
321
to a value obtained by multiplying, at multiplier
312
, the value of the A
2
bit by input data D that have been shifted one bit to the left one-bit shift circuit
301
.
The value of input-data D that have been shifted another bit to the left by bit shift circuit
302
is multiplied by the value of the A
3
bit at multiplier
313
, and this result is added to the addition result of adder
321
at adder
322
. The same calculation is then carried out by one-bit shift circuit
303
, multiplier
314
, adder circuit
323
, one-bit shift circuit
304
, multiplier
315
, adder circuit
324
, one-bit shift circuit
305
, multiplier
316
, and adder circuit
325
.
FIG. 2
shows a multiplier of a shift addition system, which is another example of the prior art. Input data are bit-shifted by n-bit shift register
401
, synchronized with a clock and outputted, and then logically ANDed with the output of multiplier circuit
402
to at AND circuit
403
. A multiplication operation is then performed by adding this result to the content of D-type flip-flop
405
at adder circuit
404
. In this case, one adder is used to carry out the addition operation because data to be shifted next are added to the addition operation results that were previously shifted (stored in D flip-flop
405
).
In the first example of the prior art, the calculation results are found by adding the results of multiplying input data D that have been shifted n bits by each of the M bits. This construction requires five adders and five bit-shift circuits for performing the process of shifting input data D one bit at a time. As a consequence, the operation is time-consuming, the circuit configuration is complex, and the circuit scale is large.
The other example of the prior art, which is a multiplier circuit of a shift addition system that is typical in the prior art, has a simple configuration. This example, however, employs a shift register and therefore requires the supply of clocks from the outside and further, requires a number of blocks of processing time equal to the number of numerical digits of the multiplier before output results can be obtained.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a decibel level adjustment device that features a simple configuration, a smaller circuit scale, and shorter processing time, and moreover, that can dynamically designate the calculation range.
The present invention is a decibel level adjustment device that is used at points where processing for digitally adjusting the level of signal amplitude is performed in a circuit that adjusts the amplitude of a signal, such as in a wireless apparatus. The present invention performs a level adjustment operation for received signals with decibels as units in accordance with a decibel control value.
In contrast with a decibel calculation circuit of the prior art that uses ordinary multiplier circuits, the decibel level adjustment device of this invention has a construction that produces a plurality of signals in which the bit width of the amplitude level of an input signal is expanded according to a received decibel control value and that produces the target signal level by adding these generated signals together.
Accordingly, this decibel level adjustment device can easily convert a signal for which amplitude adjustment is desired to output of any level by applying a decibel control value (dB). In addition, the output result can be obtained at higher speed because the number of operations is reduced.
Considering the principles of multiplication in a bit sequence, an original number is multiplied by 1/(2 to the nth power) each time the original number is shifted one bit to the right, and multiplied by 2 to the nth power when shifted one bit to the left. It is a well-known fact that any level can be produced by adding combinations of these multiples. The present invention provides a, device capable of easy decibel operation by focusing on these rules and the units of dB.
For example, 1 dB is approximately 1.12202 times the input signal and therefore can be represented by the result of adding 0-bit shift+3-bit right shift. The symbol “(2)” below indicates that a figure is in binary notation. In effect, 1 dB≈1.12202 (antilogarithm)=1.001000 (2)=1.0+0.125.
Since 2 dB is approximately 1.25893 times the input signal, it can be represented by the result of adding: 0-bit shift+2-bit right shift+6-bit right shift.
Similarly, 2 dB≈1.25893 (antilogarithm)=1.010001 [(2)]=1.0+0.25+0.01563. The values for 3, 4, and 5 dB can be found in the same way. Furthermore, −1 dB, −2 dB can also be calculated in the same way. For example, −1 is approximately 0.89125 times the input signal and therefore can be represented by the result of adding: 1-bit right shift+2-bit right shift+3-bit right shift +6-bit right shift.
Thus, −1 dB≈0.89125 (antilogarithm)=0.5+0.25+0.125+0.01563.
Based on these relationships, Table 2 shows values for control values in 1-dB units from −18 dB to +17 dB.
In the present invention, the means for shifting input data perform simultaneous processing in parallel. In addition, the means for shifting input data are not of a construction that uses shift registers and are therefore capable of high-speed operation. Moreover, the adders are capable of completing an operation in one processing unit and the processing time is therefore minimal.
In actuality, the time taken for an operation also depends on the calculation accuracy, but, as an example, even if the amount of bit-shifting for the 0-5 dB calculation group is set at as many as 6 stages, the calculation requires no more than three adders. Since the first-stage adders can perform addition in parallel, the operation can be completed in the time of two addition operations (gate operation only), and the operation is therefore extremely fast.
In the present invention, furthermore, output of any broad range can be obtained by shifting the level of input signals in parallel and then adding a shift c

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